This file controls how “info register” in gdb
this file riscv-64bit-cpu.xml controls how “info register” printing values in gdb. I tried to add one entry to it to print the “PC” value one more time, it works
RISC-V progress
挾左個vscode web版落我地個web到，開發埋自己個theme親返隻色。RISC-V asm個syntax highlight仲差少少。跟住就可以放俾澳洲啲大學生上黎係web到做RISC-V coding，simulator我部server應該頂到200-500人。
支持本土, 寫Program用香港人嘅字體
「昭源黑體」唔錯 !!! https://chiron-fonts.github.io/sans/?fbclid=IwAR1K_nmgsBYJD68yRHEMHSnfUHTjJFAGaEyBSjVrIP8DYKM0UN_7Pgtvoy8
Build vscode, host it localhost and run it in browser
https://www.barretlee.com/blog/2019/10/23/vscode-study-01-start/ Visual Studio Code 是微软推出的一款轻量级编辑器，与它一起在市场争锋的相似软件还有 Atom 和 Sublime Text，面世第二年的它只占据 7% 左右的市场，后来在短短三年时间雄踞了半壁江山，不可谓不哇塞。 发育如此强势的软件，背后到底是如何设计的，未来一段时间，我将带着你一点一点拨开她的面纱，再撩开她的裙摆。 下载源码 Visual Studio Code 简称 VSCode，需要注意的是，平时我们使用的 VSCode 那是产品，而下面我们要介绍的是源码，产品是源码的构建结果；源码使用的 MIT License，而产品使用的是这个 MICROSOFT SOFTWARE LICENSE TERMS，如果你想把 VSCode 用于商用，建议从源码构建出新的产品，而不是直接使用人家官网上提供下载链接的 VSCode Product。 官网地址是 https://code.visualstudio.com/ 源码在这里：https://github.com/microsoft/vscode。 我们先把源码 down 下来： git clone –depth 1 https://github.com/microsoft/vscode.git 由于 VSCode 项目过于活跃，提交量非常庞大，到目前为止，已经有 56,092 次提交了，建议在下载源码的时候加了一句 –depth 1，意思就是只现在最近一次 commit 的代码。 30s 后……71M，不慢。 安装依赖 在安装依赖之前，我们不妨稍微分析下 VSCode 的项目结构， ➜ vscode (master) tree -L…
Read more
Power Automate Desktop
Power Automate Desktop有好強烈嘅”Variable”氣息, 呢一點會令好多Programmer所喜愛. 加上佢對傳統Programming嘅範式有好正嘅一對一支持, 特別令Programmer容易上手, 就算係一啲初級嘅Programmer都會覺得好就手. 加上咪記黎緊會加強佢嘅SDK支持同加深自己產品線嘅整合, 所以UIPath今次玩完了.
Tutorial to use Hantek6022BE with Pulse
Step 1. Download pulseview Step 2. Make sure this button is poped out. Step 3. Install Zadig driver Step 4. Run pulseview, the device should be auto detected as “Saleae Logic”, but not “Hantek”, anyway it will works
WordPress Plugin : Google drive album
Display images google drive in your WordPRess. https://gitlab.com/quantr/wordpress/google-drive-album
Antlr parses verilog
Default antlr’s verilog grammar can’t parse verilog right, i modified a little bit to make it parse my verilog files. Here is the modified grammar https://gitlab.com/quantr/toolchain/quantr-verilog-tool/-/blob/master/src/main/java/hk/quantr/quantrverilogtool/antlr/Verilog2001.g4
Never use Baidu Cloud Disk
Simple reaons, upload is fast, download only. few ten KB/s. It looks like Baidu don’t want you to download your file, locking you in forever
RISC-V 64 bits XV kernel insturctions
addaddiaddiwaddwamoadd.damoadd.wamoadd.w.rlamoswap.wamoswap.w.aqandandiauipcbeqbeqzbgebgeubgezbgtzblezbltbltubltzbnebnezc.addc.lic.luic.mvc.nopc.sllic.slli64c.srai64csrccsrcic.srli64csrrcsrrccsrrcicsrrscsrrsicsrrwcsrrwicsrscsrwdivuwebreakecallfadd.qfadd.sfdiv.dfdiv.sfencefldflqflwfmadd.dfmadd.sfmsub.dfmsub.qfmsub.sfnmadd.dfnmadd.qfnmadd.sfnmsub.dfnmsub.qfnmsub.sformatfsdfswjjaljalrjrlblbuldlhlhuliluilwlwumretmulmulwmvnegnegwnopnotororiremuwretsbsdsectionseqzsext.wsfence.vmashsllsllislliwsllwsltsltisltiusltusltzsnezsraisraiwsretsrlsrlisrliwsrlwsubsubwswunimpxorxori
self-made tool for risc-v development
Another self-made tool for risc-v development, it is a vcd file dumper. With our own dumper, we can record the behavior of another risc-v, so we can cross check our risc-v correctless much more efficient.
Running 64- and 32-bit RISC-V Linux on QEMU
https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-qemu.html Running 64- and 32-bit RISC-V Linux on QEMU This is a “hello world” example of booting Linux on RISC-V QEMU. This guide covers some basic steps to get Linux running on RISC-V. It is recomended that if you are interested in a specific distrubution you follow their steps. For example if you are interested…
Read more
logic gate呢一層
我地平時用嘅variable，如果化到落logic gate呢一層，你無法找到佢嘅真身，佢亦都好可能同其它variable所化生嘅logic gate交織埋一齊，你亦都無可能找到佢確實嘅存在嘅時間，一切好虛無，但有其功用。呢個係coding體驗空性嘅其中一個睇法。而家啲programmer執著玩排位玩放位玩lang玩framework，真係好可憐。
New book to read: Sql server wait statistics
Learn more advanced skills for sharepoint tuning from sql server point of view.
GD32 RISC-V registers
===== RISC-V Registers(0) zero (/32)(1) ra (/32)(2) sp (/32)(3) gp (/32)(4) tp (/32)(5) t0 (/32)(6) t1 (/32)(7) t2 (/32)(8) fp (/32)(9) s1 (/32)(10) a0 (/32)(11) a1 (/32)(12) a2 (/32)(13) a3 (/32)(14) a4 (/32)(15) a5 (/32)(16) a6 (/32)(17) a7 (/32)(18) s2 (/32)(19) s3 (/32)(20) s4 (/32)(21) s5 (/32)(22) s6 (/32)(23) s7 (/32)(24) s8 (/32)(25) s9 (/32)(26)…
Read more
Good progress on RISC-V simulator development
We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples.
