Category Archives: Computer Engineering
Openlane + wsl2 : repository does not exist or may require 'docker login'
when you have this problem 2022/01/01
Openlane init files
If run fail, have to remove the "runs" folder before rerun, otherwise same error will be shown initProject.sh runProject.sh my_design.v config.tcl 2021/12/31
Arithmetic Circuits & Multipliers
https://web.mit.edu/6.111/www/f2016/handouts/L08_4.pdf 2021/12/12
HLS
Synthesis-ed part of XV6 into Verilog 2021/10/13
Good web to learn RISC-V interrupt
https://github-wiki-see.page/m/ianchen0119/AwesomeCS/wiki/Hello%2C-OS%21 https://github-wiki-see.page/m/ianchen0119/AwesomeCS/wiki/2-5-RISC-V::%E4%B8%AD%E6%96%B7%E8%88%87%E7%95%B0%E5%B8%B8%E8%99%95%E7%90%86----PLIC-%E4%BB%8B%E7%B4%B9 https://github-wiki-see.page/m/ianchen0119/AwesomeCS/wiki/2-4-RISC-V::%E4%B8%AD%E6%96%B7%E8%88%87%E7%95%B0%E5%B8%B8%E8%99%95%E7%90%86----%E4%B8%AD%E6%96%B7%E7%AF%87 2021/08/29
RISC-V readelf may has bug on field Abbrev Offset
2021/08/05
Good electronic components book
2021/05/30
RISC-V Qemu memory mapping
https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c 2021/05/11
Minimial Arduino with ATTiny85
2021/04/17
This file controls how "info register" in gdb
this file riscv-64bit-cpu.xml controls how "info register" printing values in gdb. I tried to add one entry to it to print the "PC" value one more time, it works 2021/04/04
XV6 book March 22, 2021
2021/03/22
RISC-V progress
挾左個vscode web版落我地個web到，開發埋自己個theme親返隻色。RISC-V asm個syntax highlight仲差少少。跟住就可以放俾澳洲啲大學生上黎係web到做RISC-V coding，simulator我部server應該頂到200-500人。 2021/03/08
HK Data format - draft one
2021/03/07
Assembler listing is done
2021/03/05
Structure of a NASM Program
2021/02/14
Tutorial to use Hantek6022BE with Pulse
Step 1. Download pulseview Step 2. Make sure this button is poped out. Step 3. Install Zadig driver Step 4. Run pulseview, the device should be auto detected as "Saleae Logic", but not "Hantek", anyway it will works 2021/02/13
INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986
INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 2021/02/05
RISC-V CPU verilog testbench is good now
2021/01/31
Antlr parses verilog
Default antlr's verilog grammar can't parse verilog right, i modified a little bit to make it parse my verilog files. Here is the modified grammar https://gitlab.com/quantr/toolchain/quantr-verilog-tool/-/blob/master/src/main/java/hk/quantr/quantrverilogtool/antlr/Verilog2001.g4 2021/01/30
CPU testbench同assembler testbench而家link埋
它可以幫手check下cpu decode有無錯了 2021/01/15
RISC-V 64 bits XV kernel insturctions
addaddiaddiwaddwamoadd.damoadd.wamoadd.w.rlamoswap.wamoswap.w.aqandandiauipcbeqbeqzbgebgeubgezbgtzblezbltbltubltzbnebnezc.addc.lic.luic.mvc.nopc.sllic.slli64c.srai64csrccsrcic.srli64csrrcsrrccsrrcicsrrscsrrsicsrrwcsrrwicsrscsrwdivuwebreakecallfadd.qfadd.sfdiv.dfdiv.sfencefldflqflwfmadd.dfmadd.sfmsub.dfmsub.qfmsub.sfnmadd.dfnmadd.qfnmadd.sfnmsub.dfnmsub.qfnmsub.sformatfsdfswjjaljalrjrlblbuldlhlhuliluilwlwumretmulmulwmvnegnegwnopnotororiremuwretsbsdsectionseqzsext.wsfence.vmashsllsllislliwsllwsltsltisltiusltusltzsnezsraisraiwsretsrlsrlisrliwsrlwsubsubwswunimpxorxori 2020/12/31
self-made tool for risc-v development
Another self-made tool for risc-v development, it is a vcd file dumper. With our own dumper, we can record the behavior of another risc-v, so we can cross check our risc-v correctless much more efficient. 2020/12/29
Kernel Studio dev progress
2020/11/12
Running 64- and 32-bit RISC-V Linux on QEMU
https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-qemu.html Running 64- and 32-bit RISC-V Linux on QEMU This is a “hello world” example of booting Linux on RISC-V QEMU. This guide covers some basic steps to get Linux running on RISC-V. It is recomended that if you are interested in a specific distrubution you follow their steps. For example if you are interested […] 2020/11/10
XF6 kernel use these instructions
2020/11/10
Our RISC-V simulator interface
2020/10/29
GD32 RISC-V registers
===== RISC-V Registers(0) zero (/32)(1) ra (/32)(2) sp (/32)(3) gp (/32)(4) tp (/32)(5) t0 (/32)(6) t1 (/32)(7) t2 (/32)(8) fp (/32)(9) s1 (/32)(10) a0 (/32)(11) a1 (/32)(12) a2 (/32)(13) a3 (/32)(14) a4 (/32)(15) a5 (/32)(16) a6 (/32)(17) a7 (/32)(18) s2 (/32)(19) s3 (/32)(20) s4 (/32)(21) s5 (/32)(22) s6 (/32)(23) s7 (/32)(24) s8 (/32)(25) s9 (/32)(26) […] 2020/09/06
RISC-V objdump disassemble bug
2020/08/28
Good progress on RISC-V simulator development
We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples. 2020/08/27
I think RISC-V gas has bug
Compiling instruction "csrrci x1,ucause,0x00" produce no bytes 2020/08/26
RISC-V progress
RISC-V encoding part & decoding part of assembler and disassembler for imc are done. 2020/07/20
RISC-V disassembler can decode whole RV32IC
I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF. 2020/07/04
Hour of code 2020/06/27 RISC-V assembly
2020/06/30
riscv green card is wrong
c.sub should be CA format, not CR 2020/06/21
Arduino output sine wave, it works
My Arduino board has built-in DAC, can output sine wave. 2020/06/14
compressed instructions is working in testbench web
2020/06/13
Can disasm RISC-V code from ELF
2020/06/07
ASSEMBLER MEETUP #42, 2020/05/30
Doing RISC-V assembler, this is our first decode screen 2020/05/30
RISC-V Instruction set naming
2020/05/30
short-term risc-v plan 20200523
2020/05/23
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