2021/01/31

Default antlr's verilog grammar can't parse verilog right, i modified a little bit to make it parse my verilog files. Here is the modified grammar https://gitlab.com/quantr/toolchain/quantr-verilog-tool/-/blob/master/src/main/java/hk/quantr/quantrverilogtool/antlr/Verilog2001.g4 2021/01/30

它可以幫手check下cpu decode有無錯了 2021/01/15

addaddiaddiwaddwamoadd.damoadd.wamoadd.w.rlamoswap.wamoswap.w.aqandandiauipcbeqbeqzbgebgeubgezbgtzblezbltbltubltzbnebnezc.addc.lic.luic.mvc.nopc.sllic.slli64c.srai64csrccsrcic.srli64csrrcsrrccsrrcicsrrscsrrsicsrrwcsrrwicsrscsrwdivuwebreakecallfadd.qfadd.sfdiv.dfdiv.sfencefldflqflwfmadd.dfmadd.sfmsub.dfmsub.qfmsub.sfnmadd.dfnmadd.qfnmadd.sfnmsub.dfnmsub.qfnmsub.sformatfsdfswjjaljalrjrlblbuldlhlhuliluilwlwumretmulmulwmvnegnegwnopnotororiremuwretsbsdsectionseqzsext.wsfence.vmashsllsllislliwsllwsltsltisltiusltusltzsnezsraisraiwsretsrlsrlisrliwsrlwsubsubwswunimpxorxori 2020/12/31

Another self-made tool for risc-v development, it is a vcd file dumper. With our own dumper, we can record the behavior of another risc-v, so we can cross check our risc-v correctless much more efficient. 2020/12/29

2020/11/12

https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-qemu.html Running 64- and 32-bit RISC-V Linux on QEMU This is a “hello world” example of booting Linux on RISC-V QEMU. This guide covers some basic steps to get Linux running on RISC-V. It is recomended that if you are interested in a specific distrubution you follow their steps. For example if you are interested […] 2020/11/10

2020/11/10

2020/10/29

===== RISC-V Registers(0) zero (/32)(1) ra (/32)(2) sp (/32)(3) gp (/32)(4) tp (/32)(5) t0 (/32)(6) t1 (/32)(7) t2 (/32)(8) fp (/32)(9) s1 (/32)(10) a0 (/32)(11) a1 (/32)(12) a2 (/32)(13) a3 (/32)(14) a4 (/32)(15) a5 (/32)(16) a6 (/32)(17) a7 (/32)(18) s2 (/32)(19) s3 (/32)(20) s4 (/32)(21) s5 (/32)(22) s6 (/32)(23) s7 (/32)(24) s8 (/32)(25) s9 (/32)(26) […] 2020/09/06

2020/08/28

We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples. 2020/08/27

Compiling instruction "csrrci x1,ucause,0x00" produce no bytes 2020/08/26

RISC-V encoding part & decoding part of assembler and disassembler for imc are done. 2020/07/20

I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF. 2020/07/04

2020/06/30

c.sub should be CA format, not CR 2020/06/21

My Arduino board has built-in DAC, can output sine wave. 2020/06/14

2020/06/13

2020/06/07

Doing RISC-V assembler, this is our first decode screen 2020/05/30

2020/05/30

2020/05/23

Used near 6 hours to fix my netbeans-antlr plugin. I have to remember these: Netbeans build in antlr library have to in-sync with the antlr i am using in my pluging. If they in different version, unexpected result will come out. In windows, if antlr grammar has some mistakes (I meant not problems, your grammar […] 2020/05/09

added RISC-V supports to our testbench portal 2020/05/09

Let's do some real experiments on these boards: https://item.taobao.com/item.htm?spm=a230r.1.14.201.65363b3cWNnt8y&id=609421832198&ns=1&abbucket=1#detail https://item.taobao.com/item.htm?spm=a230r.1.14.213.65363b3cWNnt8y&id=606277334580&ns=1&abbucket=1#detail 2020/05/04

2020/05/03

2020/04/27

We agreed to put x86 and risc-v assembler code into one project, so up one level for the java package, make it ready to stuck in risc-v code I will write the first risc-v assembly grammar and upgrade www.quantr.hk/asmweb to support risc-v test cases Learning vscode extension development, make myself ready to create a debugger […] 2020/04/11

Only 42 instructons are wrong. We are close to first milestone. Will study "Island Grammar", hope it is the way to embed other antlr grammar from the main one. 2020/03/22

Still working on the Antlr grammar to supports "Label" Very naive skillset on Antlr, just bouht the english version of this book, re-read it again. Chinese one not very comfortable to read. We think we can complete the first release of the assembler within 3 months. 2020/03/07

As usual, meet in Festival Walk, sync-ed up our verilog skill, stuck in the "imm | label" to grammar. Only 64 instructions left. 2020/02/16

2020/02/14

Fixed all wrong testcases excepts ptwrite Only 87 wrong instructions are wrong encoding now 2020/02/02

Nothing special, still doing the "jump/call label", i can get the information (line number & offset) i need 2020/02/02

Peter : Adding support to "Label". Rest of people keep encoding x86 instructions. 2020/01/19

Desmond completed encoded all "OR" instructions, that proves the encoding method is mature. We heading toward our first milestone, complete encode all intel basic instructions. Peter has added all test case. To see our progress, go to http://www.quantr.hk/asmweb 2020/01/02

http://www.hantek.com/en/productdetail_153.html 2019/12/15

Good progress on shorten the grammar file. Desmond join the translation. Peter pickup the pe generator task. 2019/12/14

2019/12/07