CPU由Soft core變Hard core的步驟

CPU由Soft core變Hard core的步驟

2019/04/17 Programming 0

(Disclaimer: This might not be completely accurate since my experience in ASIC design is only that I took a course in integrated circuits a few years ago where we designed a small analog ASIC, basically just an op-amp).

My understanding of the process for taking verilog and making it into an ASIC is something like:

  • Verify the verilog works in an FPGA first.
  • Convert the verilog into equivalent logic gates.
  • If you don’t have a library with designs for the logic gates, you need to design the logic gates for the ASIC process you will be using.
  • Place the logic gates in the design.
  • Connect the logic gates with metal.
  • Add pads in the design for external connections.
  • Run lots of simulations to verify that the design you’ve made is equivalent to the verilog you started with.
  • Order the chips from an ASIC fab.
  • Either wirebond the chips to your PCB (common during early testing), or have a factory package the chips into some standard package like QFN or BGA.
  • Test that the MCU works as intended.

Regarding pricing:

It seems that MOSIS no longer has a public pricelist, but found this instead: https://www.cmc.ca/en/WhatWeOffer/Make/FabPricing.aspx .

Pricing for your whole MCU depends on how big you make it. Which is something to take into account, for example the peer reviewed pricing on the above link: TSMC 0.18um: $300/mm2, TSMC 0.35um: $200/mm2 => 0.18um process is cheaper because the chip will be smaller.


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