SEMU call graph
This graph generated by graphviz, helping students easier understand Professor Jim Huang’s SEMU RISC-V emulator
Export our data structure into logisim
Created the library to export our data structure into logisim, https://gitlab.com/quantr/eda/logisim-library , part of our EDA tool
Good HDL synthesis book
The first step of logic synthesis is call “HDL synthesis”, converting verilog into raw netlist. http://ebook.pldworld.com/_eBook/FPGA%EF%BC%8FHDL/-Eng-/Verilog%20HDL%20Synthesis.%20A%20Practical%20Primet%20%28Bhasker%29.pdf