import chisel3._
import chisel3.util._
import _root_.circt.stage.ChiselStage

class MyRam extends Module {
  val io = IO(new Bundle {
    val addr = Input(UInt(8.W))
    val dataIn = Input(UInt(8.W))
    val dataOut = Output(UInt(8.W))
    val write = Input(Bool())
  })

  val symcMem = SyncReadMem(256, UInt(8.W))
  val initDone = RegInit(false.B)

  when(!initDone) {
    io.dataOut := 0.U
    initDone := true.B
  }.otherwise {
    io.dataOut := DontCare // Ensure dataOut is not driven by default
    when(io.write) {
      symcMem.write(io.addr, io.dataIn)
    }.otherwise {
      io.dataOut := symcMem.read(io.addr)
    }
  }
}

object MyMain extends App {
  println(
    ChiselStage.emitSystemVerilog(
      gen = new MyRam,
      firtoolOpts = Array("-disable-all-randomization")
    )
  )
}

import chisel3._
import chisel3.util._
import _root_.circt.stage.ChiselStage

class MyRam extends Module {
  val io = IO(new Bundle {
    val addr = Input(UInt(8.W))
    val dataIn = Input(UInt(8.W))
    val dataOut = Output(UInt(8.W))
    val write = Input(Bool())
  })
  io.dataOut := DontCare

  val symcMem = SyncReadMem(256, UInt(8.W))
  when(io.write) {
    symcMem.write(io.addr, io.dataIn)
  }.otherwise {
    io.dataOut := symcMem.read(io.addr)
  }
}

object MyMain extends App {
  println(
    ChiselStage.emitSystemVerilog(
      gen = new MyRam,
      firtoolOpts = Array("-disable-all-randomization")
    )
  )
}