Author: admin

Tutorial to use Hantek6022BE with Pulse

Step 1. Download pulseview Step 2. Make sure this button is poped out. Step 3. Install Zadig driver Step 4. Run pulseview, the device should be auto detected as “Saleae Logic”, but not “Hantek”, anyway it will works


2021/02/13 0

WordPress Plugin : Google drive album

Display images google drive in your WordPRess. https://gitlab.com/quantr/wordpress/google-drive-album


2021/02/06 0

INTEL 80386 PROGRAMMER’S REFERENCE MANUAL 1986

INTEL 80386 PROGRAMMER’S REFERENCE MANUAL 1986


2021/02/05 0

Antlr parses verilog

Default antlr’s verilog grammar can’t parse verilog right, i modified a little bit to make it parse my verilog files. Here is the modified grammar https://gitlab.com/quantr/toolchain/quantr-verilog-tool/-/blob/master/src/main/java/hk/quantr/quantrverilogtool/antlr/Verilog2001.g4


2021/01/30 0

Never use Baidu Cloud Disk

Simple reaons, upload is fast, download only. few ten KB/s. It looks like Baidu don’t want you to download your file, locking you in forever


2021/01/25 0

CPU testbench同assembler testbench而家link埋

它可以幫手check下cpu decode有無錯了


2021/01/15 0

RISC-V 64 bits XV kernel insturctions

addaddiaddiwaddwamoadd.damoadd.wamoadd.w.rlamoswap.wamoswap.w.aqandandiauipcbeqbeqzbgebgeubgezbgtzblezbltbltubltzbnebnezc.addc.lic.luic.mvc.nopc.sllic.slli64c.srai64csrccsrcic.srli64csrrcsrrccsrrcicsrrscsrrsicsrrwcsrrwicsrscsrwdivuwebreakecallfadd.qfadd.sfdiv.dfdiv.sfencefldflqflwfmadd.dfmadd.sfmsub.dfmsub.qfmsub.sfnmadd.dfnmadd.qfnmadd.sfnmsub.dfnmsub.qfnmsub.sformatfsdfswjjaljalrjrlblbuldlhlhuliluilwlwumretmulmulwmvnegnegwnopnotororiremuwretsbsdsectionseqzsext.wsfence.vmashsllsllislliwsllwsltsltisltiusltusltzsnezsraisraiwsretsrlsrlisrliwsrlwsubsubwswunimpxorxori


2020/12/31 0

self-made tool for risc-v development

Another self-made tool for risc-v development, it is a vcd file dumper. With our own dumper, we can record the behavior of another risc-v, so we can cross check our risc-v correctless much more efficient.


2020/12/29 0

原子哥塊fpga非常唔錯,份doc好掂

份doc過千頁,跟住做毫無難度,好過”特權同學”好多,特權份doc基本上係搞笑,完全唔齊。


2020/12/27 0

Running 64- and 32-bit RISC-V Linux on QEMU

https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-qemu.html Running 64- and 32-bit RISC-V Linux on QEMU This is a “hello world” example of booting Linux on RISC-V QEMU. This guide covers some basic steps to get Linux running on RISC-V. It is recomended that if you are interested in a specific distrubution you follow their steps. For example if you are interested…
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2020/11/10 0

logic gate呢一層

我地平時用嘅variable,如果化到落logic gate呢一層,你無法找到佢嘅真身,佢亦都好可能同其它variable所化生嘅logic gate交織埋一齊,你亦都無可能找到佢確實嘅存在嘅時間,一切好虛無,但有其功用。呢個係coding體驗空性嘅其中一個睇法。而家啲programmer執著玩排位玩放位玩lang玩framework,真係好可憐。


2020/10/27 0

New book to read: Sql server wait statistics

Learn more advanced skills for sharepoint tuning from sql server point of view.


2020/10/24 0

GD32 RISC-V registers

===== RISC-V Registers(0) zero (/32)(1) ra (/32)(2) sp (/32)(3) gp (/32)(4) tp (/32)(5) t0 (/32)(6) t1 (/32)(7) t2 (/32)(8) fp (/32)(9) s1 (/32)(10) a0 (/32)(11) a1 (/32)(12) a2 (/32)(13) a3 (/32)(14) a4 (/32)(15) a5 (/32)(16) a6 (/32)(17) a7 (/32)(18) s2 (/32)(19) s3 (/32)(20) s4 (/32)(21) s5 (/32)(22) s6 (/32)(23) s7 (/32)(24) s8 (/32)(25) s9 (/32)(26)…
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2020/09/06 0

Good progress on RISC-V simulator development

We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples.


2020/08/27 0

I think RISC-V gas has bug

Compiling instruction “csrrci x1,ucause,0x00” produce no bytes


2020/08/26 0

New Book


2020/08/23 0

SharePoint can’t login ad user (Resolved)

https://www.mssqltips.com/sqlservertip/3889/resolving-sharepoint-application-authentication-error-login-failed/


2020/08/19 0

RISC-V progress

RISC-V encoding part & decoding part of assembler and disassembler for imc are done.


2020/07/20 0

RISC-V disassembler can decode whole RV32IC

I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF.


2020/07/04 0

Netbeans antlr plugin can format antlr source file

My netbeans antlr plugin finally can format antlr source code


2020/06/26 0

riscv green card is wrong

c.sub should be CA format, not CR


2020/06/21 0

Arduino output sine wave, it works

My Arduino board has built-in DAC, can output sine wave.


2020/06/14 0

ASSEMBLER MEETUP #42, 2020/05/30

Doing RISC-V assembler, this is our first decode screen


2020/05/30 0