Category: Computer Engineering

RISC-V objdump disassemble bug

Good progress on RISC-V simulator development

We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples.

I think RISC-V gas has bug

Compiling instruction “csrrci x1,ucause,0x00” produce no bytes

RISC-V progress

RISC-V encoding part & decoding part of assembler and disassembler for imc are done.

RISC-V disassembler can decode whole RV32IC

I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF.

Hour of code 2020/06/27 RISC-V assembly

Arduino output sine wave, it works

My Arduino board has built-in DAC, can output sine wave.

compressed instructions is working in testbench web

Can disasm RISC-V code from ELF

ASSEMBLER MEETUP #42, 2020/05/30

Doing RISC-V assembler, this is our first decode screen

short-term risc-v plan 20200523

ASSEMBLER MEETUP #41, 2020/05/09

added RISC-V supports to our testbench portal

RISC-V boards arrived

Let’s do some real experiments on these boards: https://item.taobao.com/item.htm?spm=a230r.1.14.201.65363b3cWNnt8y&id=609421832198&ns=1&abbucket=1#detail https://item.taobao.com/item.htm?spm=a230r.1.14.213.65363b3cWNnt8y&id=606277334580&ns=1&abbucket=1#detail

Conquer the Sigrok decoder development

小組討論一下RISC-V的assembly東西

ASSEMBLER MEETUP #37, 2020/04/11

We agreed to put x86 and risc-v assembler code into one project, so up one level for the java package, make it ready to stuck in risc-v code I will write the first risc-v assembly grammar and upgrade www.quantr.hk/asmweb to support risc-v test cases Learning vscode extension development, make myself ready to create a debugger…
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Assembler Meetup #34, 2020/03/21

Only 42 instructons are wrong. We are close to first milestone. Will study “Island Grammar”, hope it is the way to embed other antlr grammar from the main one.

Assembler Meetup #32, 2020/03/07

Still working on the Antlr grammar to supports “Label” Very naive skillset on Antlr, just bouht the english version of this book, re-read it again. Chinese one not very comfortable to read. We think we can complete the first release of the assembler within 3 months.

Assembler Meetup #30, 2020/02/15

As usual, meet in Festival Walk, sync-ed up our verilog skill, stuck in the “imm | label” to grammar. Only 64 instructions left.

Assembler Meetup #27, 2020/01/18

Peter : Adding support to “Label”. Rest of people keep encoding x86 instructions.

Assembler Meetup #26, 2019/12/28

Desmond completed encoded all “OR” instructions, that proves the encoding method is mature. We heading toward our first milestone, complete encode all intel basic instructions. Peter has added all test case. To see our progress, go to http://www.quantr.hk/asmweb

推薦一個國產示波器連logic analyzer

http://www.hantek.com/en/productdetail_153.html

Assembler Meetup #24, 2019/12/14

Good progress on shorten the grammar file. Desmond join the translation. Peter pickup the pe generator task.

stepfpga simple project setup

參觀港產FPGA生產商Efinix

參觀Efinix公司, 一定要支持一下香港公司

Verilog syntax conflict

I guess syntax conflict or not is depend on how fpga vendor implement their verilog compile, nothing about the verilog language specification

Assembler Dev #16 2019/10/12

We finalize our error handling method, in both antlr grammar and java instruction “ADC” fully encoded, but still some combination mis-encoded. That means nasm don’t encode it, but we do https://www.quantr.hk/asmweb , our new testing site is launched

Assembler Dev #16 is cancelled

It is because of Carrie Lam

Assembler dev meeting #15

2019/09/28 meeting in cityu. We soonly clear up all combination of ADC instruction. Updated the testing web https://www.quantr.hk/asmweb