Openlane + wsl2 : repository does not exist or may require ‘docker login’
when you have this problem
Openlane init files
If run fail, have to remove the “runs” folder before rerun, otherwise same error will be shown initProject.sh runProject.sh my_design.v config.tcl
Good web to learn RISC-V interrupt
https://github-wiki-see.page/m/ianchen0119/AwesomeCS/wiki/Hello%2C-OS%21 https://github-wiki-see.page/m/ianchen0119/AwesomeCS/wiki/2-5-RISC-V::%E4%B8%AD%E6%96%B7%E8%88%87%E7%95%B0%E5%B8%B8%E8%99%95%E7%90%86—-PLIC-%E4%BB%8B%E7%B4%B9 https://github-wiki-see.page/m/ianchen0119/AwesomeCS/wiki/2-4-RISC-V::%E4%B8%AD%E6%96%B7%E8%88%87%E7%95%B0%E5%B8%B8%E8%99%95%E7%90%86—-%E4%B8%AD%E6%96%B7%E7%AF%87
This file controls how “info register” in gdb
this file riscv-64bit-cpu.xml controls how “info register” printing values in gdb. I tried to add one entry to it to print the “PC” value one more time, it works
RISC-V progress
挾左個vscode web版落我地個web到，開發埋自己個theme親返隻色。RISC-V asm個syntax highlight仲差少少。跟住就可以放俾澳洲啲大學生上黎係web到做RISC-V coding，simulator我部server應該頂到200-500人。
Tutorial to use Hantek6022BE with Pulse
Step 1. Download pulseview Step 2. Make sure this button is poped out. Step 3. Install Zadig driver Step 4. Run pulseview, the device should be auto detected as “Saleae Logic”, but not “Hantek”, anyway it will works
Antlr parses verilog
Default antlr’s verilog grammar can’t parse verilog right, i modified a little bit to make it parse my verilog files. Here is the modified grammar https://gitlab.com/quantr/toolchain/quantr-verilog-tool/-/blob/master/src/main/java/hk/quantr/quantrverilogtool/antlr/Verilog2001.g4
RISC-V 64 bits XV kernel insturctions
addaddiaddiwaddwamoadd.damoadd.wamoadd.w.rlamoswap.wamoswap.w.aqandandiauipcbeqbeqzbgebgeubgezbgtzblezbltbltubltzbnebnezc.addc.lic.luic.mvc.nopc.sllic.slli64c.srai64csrccsrcic.srli64csrrcsrrccsrrcicsrrscsrrsicsrrwcsrrwicsrscsrwdivuwebreakecallfadd.qfadd.sfdiv.dfdiv.sfencefldflqflwfmadd.dfmadd.sfmsub.dfmsub.qfmsub.sfnmadd.dfnmadd.qfnmadd.sfnmsub.dfnmsub.qfnmsub.sformatfsdfswjjaljalrjrlblbuldlhlhuliluilwlwumretmulmulwmvnegnegwnopnotororiremuwretsbsdsectionseqzsext.wsfence.vmashsllsllislliwsllwsltsltisltiusltusltzsnezsraisraiwsretsrlsrlisrliwsrlwsubsubwswunimpxorxori
self-made tool for risc-v development
Another self-made tool for risc-v development, it is a vcd file dumper. With our own dumper, we can record the behavior of another risc-v, so we can cross check our risc-v correctless much more efficient.
Running 64- and 32-bit RISC-V Linux on QEMU
https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-qemu.html Running 64- and 32-bit RISC-V Linux on QEMU This is a “hello world” example of booting Linux on RISC-V QEMU. This guide covers some basic steps to get Linux running on RISC-V. It is recomended that if you are interested in a specific distrubution you follow their steps. For example if you are interested…
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GD32 RISC-V registers
===== RISC-V Registers(0) zero (/32)(1) ra (/32)(2) sp (/32)(3) gp (/32)(4) tp (/32)(5) t0 (/32)(6) t1 (/32)(7) t2 (/32)(8) fp (/32)(9) s1 (/32)(10) a0 (/32)(11) a1 (/32)(12) a2 (/32)(13) a3 (/32)(14) a4 (/32)(15) a5 (/32)(16) a6 (/32)(17) a7 (/32)(18) s2 (/32)(19) s3 (/32)(20) s4 (/32)(21) s5 (/32)(22) s6 (/32)(23) s7 (/32)(24) s8 (/32)(25) s9 (/32)(26)…
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Good progress on RISC-V simulator development
We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples.
RISC-V progress
RISC-V encoding part & decoding part of assembler and disassembler for imc are done.
RISC-V disassembler can decode whole RV32IC
I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF.
