Category: Computer Engineering

RISC-V disassembler can decode whole RV32IC

I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF.

2020/07/04 0

riscv green card is wrong

c.sub should be CA format, not CR

2020/06/21 0

Arduino output sine wave, it works

My Arduino board has built-in DAC, can output sine wave.

2020/06/14 0

ASSEMBLER MEETUP #42, 2020/05/30

Doing RISC-V assembler, this is our first decode screen

2020/05/30 0

6 hours to fix my antlr netbeans plugin

Used near 6 hours to fix my netbeans-antlr plugin. I have to remember these: Netbeans build in antlr library have to in-sync with the antlr i am using in my pluging. If they in different version, unexpected result will come out. In windows, if antlr grammar has some mistakes (I meant not problems, your grammar…
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2020/05/09 0

ASSEMBLER MEETUP #41, 2020/05/09

added RISC-V supports to our testbench portal

2020/05/09 0

RISC-V boards arrived

Let’s do some real experiments on these boards:

2020/05/04 0

ASSEMBLER MEETUP #37, 2020/04/11

We agreed to put x86 and risc-v assembler code into one project, so up one level for the java package, make it ready to stuck in risc-v code I will write the first risc-v assembly grammar and upgrade to support risc-v test cases Learning vscode extension development, make myself ready to create a debugger…
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2020/04/11 0

Assembler Meetup #34, 2020/03/21

Only 42 instructons are wrong. We are close to first milestone. Will study “Island Grammar”, hope it is the way to embed other antlr grammar from the main one.

2020/03/22 0

Assembler Meetup #32, 2020/03/07

Still working on the Antlr grammar to supports “Label” Very naive skillset on Antlr, just bouht the english version of this book, re-read it again. Chinese one not very comfortable to read. We think we can complete the first release of the assembler within 3 months.

2020/03/07 0

Assembler Meetup #30, 2020/02/15

As usual, meet in Festival Walk, sync-ed up our verilog skill, stuck in the “imm | label” to grammar. Only 64 instructions left.

2020/02/16 0

Assembler Meetup #29, 2020/02/01

Fixed all wrong testcases excepts ptwrite Only 87 wrong instructions are wrong encoding now

2020/02/02 0

Assembler Meetup #28, 2020/01/25

Nothing special, still doing the “jump/call label”, i can get the information (line number & offset) i need

2020/02/02 0

Assembler Meetup #27, 2020/01/18

Peter : Adding support to “Label”. Rest of people keep encoding x86 instructions.

2020/01/19 0

Assembler Meetup #26, 2019/12/28

Desmond completed encoded all “OR” instructions, that proves the encoding method is mature. We heading toward our first milestone, complete encode all intel basic instructions. Peter has added all test case. To see our progress, go to

2020/01/02 0

推薦一個國產示波器連logic analyzer

2019/12/15 0

Assembler Meetup #24, 2019/12/14

Good progress on shorten the grammar file. Desmond join the translation. Peter pickup the pe generator task.

2019/12/14 0

Assembler Meetup #23, 2019/12/07

Meet in MongKok. Mainly shorten the grammar. Jenny confirmed each instruction can be translated by same five functions. We confirmed if instruction has only one operand, we have to add byte/word/dword/qword, e.g.: inc byte [ax] And some instructions such as call doesn’t support all four combinations of byte/word/dword/qword, this “call byte [ax]” will report error…
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2019/12/07 0


參觀Efinix公司, 一定要支持一下香港公司

2019/12/01 0

Assembler Meetup #22, 2019/11/30

Jenny teach me code translate Not sure our method is unify or not Trying to make the grammar file shorter and uniform

2019/11/30 0

Assembler Meetup #21, 2019/11/23

Cityu is close, we change to meet in Moko

2019/11/30 0

Verilog syntax conflict

I guess syntax conflict or not is depend on how fpga vendor implement their verilog compile, nothing about the verilog language specification

2019/11/29 0

Assembler Dev #16 2019/10/12

We finalize our error handling method, in both antlr grammar and java instruction “ADC” fully encoded, but still some combination mis-encoded. That means nasm don’t encode it, but we do , our new testing site is launched

2019/10/12 0

Getting started with RISC-V So you have heard of this RISC-V thing typically talked about in the context of microprocessors and to a lesser degree also for desktop processors. RISC-V is an open-source hardware instruction set architecture (ISA). Similarly to how X86 for Intel and AMD is a closed source ISA. Being an open-source ISA any manufacturer can…
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2019/10/05 0

Assembler Dev #16 is cancelled

It is because of Carrie Lam

2019/10/05 0

Assembler dev meeting #15

2019/09/28 meeting in cityu. We soonly clear up all combination of ADC instruction. Updated the testing web

2019/10/02 0

Assembler dev meeting #14

2019/09/21, as usual, heading to our first milestone. Enhanced the full test output, added two filters. Filter out by instruction or by error. Jenny and Kelvin is clearing the ADC instruction Desmond is extending to support Windows PE format

2019/09/22 0


Heading to goal : Our assembler our elf file directly

2019/09/21 0

Assembler dev meeting #13

2019/09/14, we met in cityu again. I finished IMM in other project . So Assembler’s parser will eat up the whole numeric string and then pass it to antlr-calculator-library, if it contains a maths expression, it return the final answer which is a number. I created another library to produce ELF output. Jenny and…
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2019/09/16 0

強烈推介, 深圳小脚丫fpga 主要好處是: 面積細 一條USB搞定, 不用其它Jtag Lattice Diamond好易上手, 至少比Quartus和Vivago更易

2019/09/08 0