Category: Computer Engineering

CPU testbench同assembler testbench而家link埋

它可以幫手check下cpu decode有無錯了

2021/01/15 0

RISC-V 64 bits XV kernel insturctions


2020/12/31 0

self-made tool for risc-v development

Another self-made tool for risc-v development, it is a vcd file dumper. With our own dumper, we can record the behavior of another risc-v, so we can cross check our risc-v correctless much more efficient.

2020/12/29 0

Running 64- and 32-bit RISC-V Linux on QEMU Running 64- and 32-bit RISC-V Linux on QEMU This is a “hello world” example of booting Linux on RISC-V QEMU. This guide covers some basic steps to get Linux running on RISC-V. It is recomended that if you are interested in a specific distrubution you follow their steps. For example if you are interested…
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2020/11/10 0

GD32 RISC-V registers

===== RISC-V Registers(0) zero (/32)(1) ra (/32)(2) sp (/32)(3) gp (/32)(4) tp (/32)(5) t0 (/32)(6) t1 (/32)(7) t2 (/32)(8) fp (/32)(9) s1 (/32)(10) a0 (/32)(11) a1 (/32)(12) a2 (/32)(13) a3 (/32)(14) a4 (/32)(15) a5 (/32)(16) a6 (/32)(17) a7 (/32)(18) s2 (/32)(19) s3 (/32)(20) s4 (/32)(21) s5 (/32)(22) s6 (/32)(23) s7 (/32)(24) s8 (/32)(25) s9 (/32)(26)…
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2020/09/06 0

Good progress on RISC-V simulator development

We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples.

2020/08/27 0

I think RISC-V gas has bug

Compiling instruction “csrrci x1,ucause,0x00” produce no bytes

2020/08/26 0

RISC-V progress

RISC-V encoding part & decoding part of assembler and disassembler for imc are done.

2020/07/20 0

RISC-V disassembler can decode whole RV32IC

I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF.

2020/07/04 0

riscv green card is wrong

c.sub should be CA format, not CR

2020/06/21 0

Arduino output sine wave, it works

My Arduino board has built-in DAC, can output sine wave.

2020/06/14 0

ASSEMBLER MEETUP #42, 2020/05/30

Doing RISC-V assembler, this is our first decode screen

2020/05/30 0

6 hours to fix my antlr netbeans plugin

Used near 6 hours to fix my netbeans-antlr plugin. I have to remember these: Netbeans build in antlr library have to in-sync with the antlr i am using in my pluging. If they in different version, unexpected result will come out. In windows, if antlr grammar has some mistakes (I meant not problems, your grammar…
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2020/05/09 0

ASSEMBLER MEETUP #41, 2020/05/09

added RISC-V supports to our testbench portal

2020/05/09 0

RISC-V boards arrived

Let’s do some real experiments on these boards:

2020/05/04 0

ASSEMBLER MEETUP #37, 2020/04/11

We agreed to put x86 and risc-v assembler code into one project, so up one level for the java package, make it ready to stuck in risc-v code I will write the first risc-v assembly grammar and upgrade to support risc-v test cases Learning vscode extension development, make myself ready to create a debugger…
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2020/04/11 0

Assembler Meetup #34, 2020/03/21

Only 42 instructons are wrong. We are close to first milestone. Will study “Island Grammar”, hope it is the way to embed other antlr grammar from the main one.

2020/03/22 0

Assembler Meetup #32, 2020/03/07

Still working on the Antlr grammar to supports “Label” Very naive skillset on Antlr, just bouht the english version of this book, re-read it again. Chinese one not very comfortable to read. We think we can complete the first release of the assembler within 3 months.

2020/03/07 0

Assembler Meetup #30, 2020/02/15

As usual, meet in Festival Walk, sync-ed up our verilog skill, stuck in the “imm | label” to grammar. Only 64 instructions left.

2020/02/16 0

Assembler Meetup #29, 2020/02/01

Fixed all wrong testcases excepts ptwrite Only 87 wrong instructions are wrong encoding now

2020/02/02 0

Assembler Meetup #28, 2020/01/25

Nothing special, still doing the “jump/call label”, i can get the information (line number & offset) i need

2020/02/02 0

Assembler Meetup #27, 2020/01/18

Peter : Adding support to “Label”. Rest of people keep encoding x86 instructions.

2020/01/19 0

Assembler Meetup #26, 2019/12/28

Desmond completed encoded all “OR” instructions, that proves the encoding method is mature. We heading toward our first milestone, complete encode all intel basic instructions. Peter has added all test case. To see our progress, go to

2020/01/02 0

推薦一個國產示波器連logic analyzer

2019/12/15 0

Assembler Meetup #24, 2019/12/14

Good progress on shorten the grammar file. Desmond join the translation. Peter pickup the pe generator task.

2019/12/14 0

Assembler Meetup #23, 2019/12/07

Meet in MongKok. Mainly shorten the grammar. Jenny confirmed each instruction can be translated by same five functions. We confirmed if instruction has only one operand, we have to add byte/word/dword/qword, e.g.: inc byte [ax] And some instructions such as call doesn’t support all four combinations of byte/word/dword/qword, this “call byte [ax]” will report error…
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2019/12/07 0


參觀Efinix公司, 一定要支持一下香港公司

2019/12/01 0