Category: Computer Engineering

Openlane init files

If run fail, have to remove the “runs” folder before rerun, otherwise same error will be shown my_design.v config.tcl

2021/12/31 0

Arithmetic Circuits & Multipliers

2021/12/12 0


Synthesis-ed part of XV6 into Verilog

2021/10/13 0

Good web to learn RISC-V interrupt—-PLIC-%E4%BB%8B%E7%B4%B9—-%E4%B8%AD%E6%96%B7%E7%AF%87

2021/08/29 0

RISC-V Qemu memory mapping

2021/05/11 0

This file controls how “info register” in gdb

this file riscv-64bit-cpu.xml controls how “info register” printing values in gdb. I tried to add one entry to it to print the “PC” value one more time, it works

2021/04/04 0

RISC-V progress

挾左個vscode web版落我地個web到,開發埋自己個theme親返隻色。RISC-V asm個syntax highlight仲差少少。跟住就可以放俾澳洲啲大學生上黎係web到做RISC-V coding,simulator我部server應該頂到200-500人。

2021/03/08 0

Tutorial to use Hantek6022BE with Pulse

Step 1. Download pulseview Step 2. Make sure this button is poped out. Step 3. Install Zadig driver Step 4. Run pulseview, the device should be auto detected as “Saleae Logic”, but not “Hantek”, anyway it will works

2021/02/13 0



2021/02/05 0

Antlr parses verilog

Default antlr’s verilog grammar can’t parse verilog right, i modified a little bit to make it parse my verilog files. Here is the modified grammar

2021/01/30 0

CPU testbench同assembler testbench而家link埋

它可以幫手check下cpu decode有無錯了

2021/01/15 0

RISC-V 64 bits XV kernel insturctions


2020/12/31 0

self-made tool for risc-v development

Another self-made tool for risc-v development, it is a vcd file dumper. With our own dumper, we can record the behavior of another risc-v, so we can cross check our risc-v correctless much more efficient.

2020/12/29 0

Running 64- and 32-bit RISC-V Linux on QEMU Running 64- and 32-bit RISC-V Linux on QEMU This is a “hello world” example of booting Linux on RISC-V QEMU. This guide covers some basic steps to get Linux running on RISC-V. It is recomended that if you are interested in a specific distrubution you follow their steps. For example if you are interested…
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2020/11/10 0

GD32 RISC-V registers

===== RISC-V Registers(0) zero (/32)(1) ra (/32)(2) sp (/32)(3) gp (/32)(4) tp (/32)(5) t0 (/32)(6) t1 (/32)(7) t2 (/32)(8) fp (/32)(9) s1 (/32)(10) a0 (/32)(11) a1 (/32)(12) a2 (/32)(13) a3 (/32)(14) a4 (/32)(15) a5 (/32)(16) a6 (/32)(17) a7 (/32)(18) s2 (/32)(19) s3 (/32)(20) s4 (/32)(21) s5 (/32)(22) s6 (/32)(23) s7 (/32)(24) s8 (/32)(25) s9 (/32)(26)…
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2020/09/06 0

Good progress on RISC-V simulator development

We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples.

2020/08/27 0

I think RISC-V gas has bug

Compiling instruction “csrrci x1,ucause,0x00” produce no bytes

2020/08/26 0

RISC-V progress

RISC-V encoding part & decoding part of assembler and disassembler for imc are done.

2020/07/20 0

RISC-V disassembler can decode whole RV32IC

I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF.

2020/07/04 0

riscv green card is wrong

c.sub should be CA format, not CR

2020/06/21 0

Arduino output sine wave, it works

My Arduino board has built-in DAC, can output sine wave.

2020/06/14 0

ASSEMBLER MEETUP #42, 2020/05/30

Doing RISC-V assembler, this is our first decode screen

2020/05/30 0