1. 一棟大廈不可能分成兩棟能完全獨立運作的大廈，但軟件通常由能獨立運作的小軟件所組成，所以有理由相信軟件工程比土木工程複雜 2. 軟件工程是內循環的，意思是用軟件A創造軟件B，之後又用軟件B改進軟件A，而土木工程是單向的，所以有理由相信軟件工程比土木工程複雜 3. 就算摩天大廈，起第一層和起第一百層的技術差不多，但軟件中不同層數的建築方法是完全不同，例如os層和web層，所以有理由相信軟件工程比土木工程複雜 4. 軟件工程中做同一件事的方法比土木工程多很多，所以有理由相信軟件工程比土木工程複雜
ERROR: Module rst_gen contains processes, which are not supported by JSON backend (run `proc` first). Edit Makefile $(TARGET).json: $(OBJS) # yosys -p “synth_ecp5 -json $@” $(OBJS) yosys -p “read_verilog -sv $<” -p “synth_ecp5 -json $@” $(OBJS)
正點原子的教程是在Keil, 如果要在STM32CubeMX裏玩UART可跟以下步驟 Step 1. Step 2. Comment the whole file Step 3. Add these 3 files from the CD Step 4. Modify usart.c , default example override fputc never works, we have to overrid _write Step 5. Add this
https://detail.tmall.com/item.htm?id=608821542489&ut_sk=1.YQ5qR5EunYQDAGcswWUaYJAm_21380790_1645025705879.Copy.ShareGlobalNavigation_1&sourceType=item&suid=5126BB92-305B-45E6-8276-4172EC31002C&un=8a0a0fd7954c2f6e4c6e4bed9157ce66&share_crt_v=1&un_site=0&spm=a2159r.13376460.0.0&tbSocialPopKey=shareItem&sp_tk=N1NJYzJlWjE5Qlo=&cpp=1&shareurl=true&short_name=h.flQxYcG&bxsign=scd65TMfrhTLdTfSFZEA2TIorerOMUxRkGPXq1CP3M21S-rVCWvUVwd-K7-LDjMP5iVdFbrvI-pqNh1QUjfy_74ZmHByWfWWbQkQ35VzPBYR0iP51drxemJkdDVH4TmnTfC&tk=7SIc2eZ19BZ%E3%80%8CFT232H/FT2232HL%E6%A8%A1%E5%9D%97USB%E8%BD%ACFIFO/SPI/I2C/JTAG/RS232%E4%B8%B2%E5%8F%A3%E6%A8%A1%E5%9D%97/%E9%AB%98%E9%80%9F%E3%80%8D&app=chrome# https://ftdichip.com/wp-content/uploads/2020/08/AN_110_Programmers_Guide_for_High_Speed_FTCJTAG_DLL-1.pdf Read PWM Pins reference : https://ftdichip.com/wp-content/uploads/2020/07/AN_184-FTDI-Device-Input-Output-Pin-States.pdf
following https://jimirobot.tw/arduino-tutorial-attiny-attiny85-uno-burn/
MRK Wifi 1010 serial is different than Nano and Uno, the usb in serial and in D13/14 are separate, so code them this way
After days of hacking, i finally found out there is a dummy driver in openocd. just ./configure –enable-dummy and run it by ./bin/openocd -c ‘interface dummy’ -c ‘adapter_khz 1’ , you can see the dummy driver is running and in the function “static int dummy_write(int tck, int tms, int tdi)”, we can manually toggle the…
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This is the tutorial to build libsigrok and pulseview in windows Download msys https://www.msys2.org/ Open “MSYS2 MinGW x64”, don’t use “MSYS2 MSYS” 3. git clone https://github.com/sigrokproject/sigrok-util.git 4. cd sigrok-utils/cross-compile/msys2 5. ./sigrok-native-msys2 prepare , it will auto install all necessary packages Compile libsigrok 6. git clone https://gitlab.com/quantr/toolchain/libsigrok.git 7. cd libsigrok 8. ./autogen.sh 9. vi configure and…
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when you have this problem
If run fail, have to remove the “runs” folder before rerun, otherwise same error will be shown initProject.sh runProject.sh my_design.v config.tcl
https://github-wiki-see.page/m/ianchen0119/AwesomeCS/wiki/Hello%2C-OS%21 https://github-wiki-see.page/m/ianchen0119/AwesomeCS/wiki/2-5-RISC-V::%E4%B8%AD%E6%96%B7%E8%88%87%E7%95%B0%E5%B8%B8%E8%99%95%E7%90%86—-PLIC-%E4%BB%8B%E7%B4%B9 https://github-wiki-see.page/m/ianchen0119/AwesomeCS/wiki/2-4-RISC-V::%E4%B8%AD%E6%96%B7%E8%88%87%E7%95%B0%E5%B8%B8%E8%99%95%E7%90%86—-%E4%B8%AD%E6%96%B7%E7%AF%87
this file riscv-64bit-cpu.xml controls how “info register” printing values in gdb. I tried to add one entry to it to print the “PC” value one more time, it works
挾左個vscode web版落我地個web到，開發埋自己個theme親返隻色。RISC-V asm個syntax highlight仲差少少。跟住就可以放俾澳洲啲大學生上黎係web到做RISC-V coding，simulator我部server應該頂到200-500人。
Step 1. Download pulseview Step 2. Make sure this button is poped out. Step 3. Install Zadig driver Step 4. Run pulseview, the device should be auto detected as “Saleae Logic”, but not “Hantek”, anyway it will works
Default antlr’s verilog grammar can’t parse verilog right, i modified a little bit to make it parse my verilog files. Here is the modified grammar https://gitlab.com/quantr/toolchain/quantr-verilog-tool/-/blob/master/src/main/java/hk/quantr/quantrverilogtool/antlr/Verilog2001.g4
addaddiaddiwaddwamoadd.damoadd.wamoadd.w.rlamoswap.wamoswap.w.aqandandiauipcbeqbeqzbgebgeubgezbgtzblezbltbltubltzbnebnezc.addc.lic.luic.mvc.nopc.sllic.slli64c.srai64csrccsrcic.srli64csrrcsrrccsrrcicsrrscsrrsicsrrwcsrrwicsrscsrwdivuwebreakecallfadd.qfadd.sfdiv.dfdiv.sfencefldflqflwfmadd.dfmadd.sfmsub.dfmsub.qfmsub.sfnmadd.dfnmadd.qfnmadd.sfnmsub.dfnmsub.qfnmsub.sformatfsdfswjjaljalrjrlblbuldlhlhuliluilwlwumretmulmulwmvnegnegwnopnotororiremuwretsbsdsectionseqzsext.wsfence.vmashsllsllislliwsllwsltsltisltiusltusltzsnezsraisraiwsretsrlsrlisrliwsrlwsubsubwswunimpxorxori
Another self-made tool for risc-v development, it is a vcd file dumper. With our own dumper, we can record the behavior of another risc-v, so we can cross check our risc-v correctless much more efficient.
https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-qemu.html Running 64- and 32-bit RISC-V Linux on QEMU This is a “hello world” example of booting Linux on RISC-V QEMU. This guide covers some basic steps to get Linux running on RISC-V. It is recomended that if you are interested in a specific distrubution you follow their steps. For example if you are interested…
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===== RISC-V Registers(0) zero (/32)(1) ra (/32)(2) sp (/32)(3) gp (/32)(4) tp (/32)(5) t0 (/32)(6) t1 (/32)(7) t2 (/32)(8) fp (/32)(9) s1 (/32)(10) a0 (/32)(11) a1 (/32)(12) a2 (/32)(13) a3 (/32)(14) a4 (/32)(15) a5 (/32)(16) a6 (/32)(17) a7 (/32)(18) s2 (/32)(19) s3 (/32)(20) s4 (/32)(21) s5 (/32)(22) s6 (/32)(23) s7 (/32)(24) s8 (/32)(25) s9 (/32)(26)…
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We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples.
