Category: Computer Engineering

This file controls how “info register” in gdb

this file riscv-64bit-cpu.xml controls how “info register” printing values in gdb. I tried to add one entry to it to print the “PC” value one more time, it works

RISC-V progress

挾左個vscode web版落我地個web到，開發埋自己個theme親返隻色。RISC-V asm個syntax highlight仲差少少。跟住就可以放俾澳洲啲大學生上黎係web到做RISC-V coding，simulator我部server應該頂到200-500人。

HK Data format – draft one

Assembler listing is done

Structure of a NASM Program

Tutorial to use Hantek6022BE with Pulse

Step 1. Download pulseview Step 2. Make sure this button is poped out. Step 3. Install Zadig driver Step 4. Run pulseview, the device should be auto detected as “Saleae Logic”, but not “Hantek”, anyway it will works

RISC-V CPU verilog testbench is good now

Antlr parses verilog

Default antlr’s verilog grammar can’t parse verilog right, i modified a little bit to make it parse my verilog files. Here is the modified grammar https://gitlab.com/quantr/toolchain/quantr-verilog-tool/-/blob/master/src/main/java/hk/quantr/quantrverilogtool/antlr/Verilog2001.g4

CPU testbench同assembler testbench而家link埋

它可以幫手check下cpu decode有無錯了

self-made tool for risc-v development

Another self-made tool for risc-v development, it is a vcd file dumper. With our own dumper, we can record the behavior of another risc-v, so we can cross check our risc-v correctless much more efficient.

Kernel Studio dev progress

RISC-V objdump disassemble bug

Good progress on RISC-V simulator development

We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples.

I think RISC-V gas has bug

Compiling instruction “csrrci x1,ucause,0x00” produce no bytes

RISC-V progress

RISC-V encoding part & decoding part of assembler and disassembler for imc are done.

RISC-V disassembler can decode whole RV32IC

I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF.

Hour of code 2020/06/27 RISC-V assembly

Arduino output sine wave, it works

My Arduino board has built-in DAC, can output sine wave.

compressed instructions is working in testbench web

Can disasm RISC-V code from ELF

ASSEMBLER MEETUP #42, 2020/05/30

Doing RISC-V assembler, this is our first decode screen

short-term risc-v plan 20200523

ASSEMBLER MEETUP #41, 2020/05/09

added RISC-V supports to our testbench portal

RISC-V boards arrived

Let’s do some real experiments on these boards: https://item.taobao.com/item.htm?spm=a230r.1.14.201.65363b3cWNnt8y&id=609421832198&ns=1&abbucket=1#detail https://item.taobao.com/item.htm?spm=a230r.1.14.213.65363b3cWNnt8y&id=606277334580&ns=1&abbucket=1#detail

Conquer the Sigrok decoder development

小組討論一下RISC-V的assembly東西

ASSEMBLER MEETUP #37, 2020/04/11

We agreed to put x86 and risc-v assembler code into one project, so up one level for the java package, make it ready to stuck in risc-v code I will write the first risc-v assembly grammar and upgrade www.quantr.hk/asmweb to support risc-v test cases Learning vscode extension development, make myself ready to create a debugger…
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Assembler Meetup #34, 2020/03/21

Only 42 instructons are wrong. We are close to first milestone. Will study “Island Grammar”, hope it is the way to embed other antlr grammar from the main one.

Assembler Meetup #32, 2020/03/07

Still working on the Antlr grammar to supports “Label” Very naive skillset on Antlr, just bouht the english version of this book, re-read it again. Chinese one not very comfortable to read. We think we can complete the first release of the assembler within 3 months.

Assembler Meetup #30, 2020/02/15

As usual, meet in Festival Walk, sync-ed up our verilog skill, stuck in the “imm | label” to grammar. Only 64 instructions left.