Good progress on RISC-V simulator development
We have good progress, finished running 3 examples successfully. Go jump in to simulate some big examples.
RISC-V progress
RISC-V encoding part & decoding part of assembler and disassembler for imc are done.
RISC-V disassembler can decode whole RV32IC
I think i can finish the RISC-V disassembler these two weeks. So far it can successfully decode RV32IC and ELF.
6 hours to fix my antlr netbeans plugin
Used near 6 hours to fix my netbeans-antlr plugin. I have to remember these: Netbeans build in antlr library have to in-sync with the antlr i am using in my pluging. If they in different version, unexpected result will come out. In windows, if antlr grammar has some mistakes (I meant not problems, your grammar…
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RISC-V boards arrived
Let’s do some real experiments on these boards: https://item.taobao.com/item.htm?spm=a230r.1.14.201.65363b3cWNnt8y&id=609421832198&ns=1&abbucket=1#detail https://item.taobao.com/item.htm?spm=a230r.1.14.213.65363b3cWNnt8y&id=606277334580&ns=1&abbucket=1#detail
ASSEMBLER MEETUP #37, 2020/04/11
We agreed to put x86 and risc-v assembler code into one project, so up one level for the java package, make it ready to stuck in risc-v code I will write the first risc-v assembly grammar and upgrade www.quantr.hk/asmweb to support risc-v test cases Learning vscode extension development, make myself ready to create a debugger…
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Assembler Meetup #34, 2020/03/21
Only 42 instructons are wrong. We are close to first milestone. Will study “Island Grammar”, hope it is the way to embed other antlr grammar from the main one.
Assembler Meetup #32, 2020/03/07
Still working on the Antlr grammar to supports “Label” Very naive skillset on Antlr, just bouht the english version of this book, re-read it again. Chinese one not very comfortable to read. We think we can complete the first release of the assembler within 3 months.
Assembler Meetup #30, 2020/02/15
As usual, meet in Festival Walk, sync-ed up our verilog skill, stuck in the “imm | label” to grammar. Only 64 instructions left.
Assembler Meetup #29, 2020/02/01
Fixed all wrong testcases excepts ptwrite Only 87 wrong instructions are wrong encoding now
Assembler Meetup #28, 2020/01/25
Nothing special, still doing the “jump/call label”, i can get the information (line number & offset) i need
Assembler Meetup #27, 2020/01/18
Peter : Adding support to “Label”. Rest of people keep encoding x86 instructions.
Assembler Meetup #26, 2019/12/28
Desmond completed encoded all “OR” instructions, that proves the encoding method is mature. We heading toward our first milestone, complete encode all intel basic instructions. Peter has added all test case. To see our progress, go to http://www.quantr.hk/asmweb
Assembler Meetup #24, 2019/12/14
Good progress on shorten the grammar file. Desmond join the translation. Peter pickup the pe generator task.
Assembler Meetup #23, 2019/12/07
Meet in MongKok. Mainly shorten the grammar. Jenny confirmed each instruction can be translated by same five functions. We confirmed if instruction has only one operand, we have to add byte/word/dword/qword, e.g.: inc byte [ax] And some instructions such as call doesn’t support all four combinations of byte/word/dword/qword, this “call byte [ax]” will report error…
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Assembler Meetup #22, 2019/11/30
Jenny teach me code translate Not sure our method is unify or not Trying to make the grammar file shorter and uniform
Verilog syntax conflict
I guess syntax conflict or not is depend on how fpga vendor implement their verilog compile, nothing about the verilog language specification
Assembler Dev #16 2019/10/12
We finalize our error handling method, in both antlr grammar and java instruction “ADC” fully encoded, but still some combination mis-encoded. That means nasm don’t encode it, but we do https://www.quantr.hk/asmweb , our new testing site is launched
Getting started with RISC-V
https://dantalion.nl/en/getting-started-with-risc-v/ So you have heard of this RISC-V thing typically talked about in the context of microprocessors and to a lesser degree also for desktop processors. RISC-V is an open-source hardware instruction set architecture (ISA). Similarly to how X86 for Intel and AMD is a closed source ISA. Being an open-source ISA any manufacturer can…
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Assembler dev meeting #15
2019/09/28 meeting in cityu. We soonly clear up all combination of ADC instruction. Updated the testing web https://www.quantr.hk/asmweb
Assembler dev meeting #14
2019/09/21, as usual, heading to our first milestone. Enhanced the full test output, added two filters. Filter out by instruction or by error. http://www.quantr.hk/wp-content/plugins/NasmWeb/public//viewOutput.php?path=/home/gitlab-runner/output/output_300588484.html Jenny and Kelvin is clearing the ADC instruction Desmond is extending https://gitlab.com/quantr/toolchain/quantr-executable-library to support Windows PE format
