Category: Computer Engineering

added RISC-V supports to our testbench portal

Let’s do some real experiments on these boards: https://item.taobao.com/item.htm?spm=a230r.1.14.201.65363b3cWNnt8y&id=609421832198&ns=1&abbucket=1#detail https://item.taobao.com/item.htm?spm=a230r.1.14.213.65363b3cWNnt8y&id=606277334580&ns=1&abbucket=1#detail

We agreed to put x86 and risc-v assembler code into one project, so up one level for the java package, make it ready to stuck in risc-v code I will write the first risc-v assembly grammar and upgrade www.quantr.hk/asmweb to support risc-v test cases Learning vscode extension development, make myself ready to create a debugger […]

Only 42 instructons are wrong. We are close to first milestone. Will study “Island Grammar”, hope it is the way to embed other antlr grammar from the main one.

Still working on the Antlr grammar to supports “Label” Very naive skillset on Antlr, just bouht the english version of this book, re-read it again. Chinese one not very comfortable to read. We think we can complete the first release of the assembler within 3 months.

As usual, meet in Festival Walk, sync-ed up our verilog skill, stuck in the “imm | label” to grammar. Only 64 instructions left.

Peter : Adding support to “Label”. Rest of people keep encoding x86 instructions.

Desmond completed encoded all “OR” instructions, that proves the encoding method is mature. We heading toward our first milestone, complete encode all intel basic instructions. Peter has added all test case. To see our progress, go to http://www.quantr.hk/asmweb

http://www.hantek.com/en/productdetail_153.html

Good progress on shorten the grammar file. Desmond join the translation. Peter pickup the pe generator task.

參觀Efinix公司, 一定要支持一下香港公司

I guess syntax conflict or not is depend on how fpga vendor implement their verilog compile, nothing about the verilog language specification

We finalize our error handling method, in both antlr grammar and java instruction “ADC” fully encoded, but still some combination mis-encoded. That means nasm don’t encode it, but we do https://www.quantr.hk/asmweb , our new testing site is launched

It is because of Carrie Lam

2019/09/28 meeting in cityu. We soonly clear up all combination of ADC instruction. Updated the testing web https://www.quantr.hk/asmweb

2019/09/21, as usual, heading to our first milestone. Enhanced the full test output, added two filters. Filter out by instruction or by error. http://www.quantr.hk/wp-content/plugins/NasmWeb/public//viewOutput.php?path=/home/gitlab-runner/output/output_300588484.html Jenny and Kelvin is clearing the ADC instruction Desmond is extending https://gitlab.com/quantr/toolchain/quantr-executable-library to support Windows PE format

https://detail.tmall.com/item.htm?id=589934876916&ali_refid=a3_430620_1006:1213910051:N:kUYNEKediVRtRcfPZeogQz+fixtE0nqV:4c45447dff14948a212296ee9fa615a2&ali_trackid=1_4c45447dff14948a212296ee9fa615a2&spm=a230r.1.14.1 主要好處是: 面積細 一條USB搞定, 不用其它Jtag Lattice Diamond好易上手, 至少比Quartus和Vivago更易

Simulation is correct

This exercise is 100% same as calculation But below one is not 100% same as calculation, it use just same components: VC + Resistors. Is multisim using brute force to guess out the voltage and current values?

Antlr C11 grammar is highly match with the C11 language specification, which is a very good news to us. https://github.com/antlr/grammars-v4/blob/master/c/C.g4

Peter updated netbeans-antlr plugin, increase our productivity: Jenny finished the REX.W translate, she keeps translating other instructions to see if our current coding facilities enough or not. Desmond is adding all the rest of the intel instructions to the grammar file, still need sometimes.