Lattice Diamond use these commands to compile my project into jed file
Synthesize Design:
synthesis -f ControlLed_impl1_lattice.synproj -gui -msgset C:/workspace/fpga/ControlLed/promote.xml
Place & Route Design:
par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/workspace/fpga/ControlLed/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF ControlLed_impl1_map.ncd ControlLed_impl1.dir/5_1.ncd ControlLed_impl1.prf
trce -v 10 -gt -sethld -sp 4 -sphld m -o ControlLed_impl1.twr -gui -msgset C:/workspace/fpga/ControlLed/promote.xml ControlLed_impl1.ncd ControlLed_impl1.prf
Export files:
tmcheck -par “ControlLed_impl1.par”
bitgen -f “ControlLed_impl1.t2b” -w “ControlLed_impl1.ncd” -jedec “ControlLed_impl1.prf”