This is a synthesis of a simple verilog program in vivado
module led_twinkle(
input sys_clk,
input sys_rst_n,
output [1:0] led
);
ila_0 peter_ila(
.clk (sys_clk),
.probe0 (led),
.probe1 (cnt)
);
reg [25:0] cnt;
assign led=(cnt<26'd1500_0000)?2'b01:2'b10;
always @(posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
cnt<=26'd0;
else if (cnt<26'd3000_0000)
cnt<=cnt+1'b1;
else
cnt<=26'd0;
end
endmodule
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2.1 (win64) Build 3414424 Sun Dec 19 10:57:22 MST 2021
| Date : Sat Oct 14 17:29:58 2023
| Host : quantr-peter-pc running 64-bit major release (build 9200)
| Command : report_utilization -file led_twinkle_utilization_synth.rpt -pb led_twinkle_utilization_synth.pb
| Design : led_twinkle
| Device : xc7a35tfgg484-2
| Speed File : -2
| Design State : Synthesized
-----------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 40 | 0 | 0 | 20800 | 0.19 |
| LUT as Logic | 40 | 0 | 0 | 20800 | 0.19 |
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 26 | 0 | 0 | 41600 | 0.06 |
| Register as Flip Flop | 26 | 0 | 0 | 41600 | 0.06 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 26 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 0 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 4 | 0 | 0 | 250 | 1.60 |
| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 20 | 0.00 |
+------------+------+-------+------------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 30 | LUT |
| FDCE | 26 | Flop & Latch |
| CARRY4 | 7 | CarryLogic |
| LUT3 | 6 | LUT |
| OBUF | 2 | IO |
| LUT4 | 2 | LUT |
| LUT1 | 2 | LUT |
| IBUF | 2 | IO |
| BUFG | 1 | Clock |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
| ila_0 | 1 |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
#-----------------------------------------------------------
# Vivado v2021.2.1 (64-bit)
# SW Build 3414424 on Sun Dec 19 10:57:22 MST 2021
# IP Build 3405791 on Sun Dec 19 15:54:35 MST 2021
# Start of session at: Sat Oct 14 17:29:24 2023
# Process ID: 11828
# Current directory: C:/workspace/led_twinkle/led_twinkle.runs/synth_1
# Command line: vivado.exe -log led_twinkle.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source led_twinkle.tcl
# Log file: C:/workspace/led_twinkle/led_twinkle.runs/synth_1/led_twinkle.vds
# Journal file: C:/workspace/led_twinkle/led_twinkle.runs/synth_1\vivado.jou
# Running On: quantr-peter-pc, OS: Windows, CPU Frequency: 3793 MHz, CPU Physical cores: 24, Host memory: 137381 MB
#-----------------------------------------------------------
source led_twinkle.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/Peter/AppData/Roaming/Xilinx/Vitis/peter1'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2021.2/data/ip'.
Command: synth_design -top led_twinkle -part xc7a35tfgg484-2
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Device 21-403] Loading part xc7a35tfgg484-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 22928
WARNING: [Synth 8-992] cnt is already implicitly declared earlier [C:/workspace/led_twinkle/led_twinkle.srcs/sources_1/new/led_twinkle.v:13]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1565.496 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'led_twinkle' [C:/workspace/led_twinkle/led_twinkle.srcs/sources_1/new/led_twinkle.v:1]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/workspace/led_twinkle/led_twinkle.srcs/sources_1/new/led_twinkle.v:7]
INFO: [Synth 8-6157] synthesizing module 'ila_0' [C:/workspace/led_twinkle/led_twinkle.runs/synth_1/.Xil/Vivado-11828-quantr-peter-pc/realtime/ila_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'ila_0' (1#1) [C:/workspace/led_twinkle/led_twinkle.runs/synth_1/.Xil/Vivado-11828-quantr-peter-pc/realtime/ila_0_stub.v:6]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'peter_ila'. This will prevent further optimization [C:/workspace/led_twinkle/led_twinkle.srcs/sources_1/new/led_twinkle.v:7]
INFO: [Synth 8-6155] done synthesizing module 'led_twinkle' (2#1) [C:/workspace/led_twinkle/led_twinkle.srcs/sources_1/new/led_twinkle.v:1]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1565.496 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1565.496 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1565.496 ; gain = 0.000
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1565.496 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [c:/workspace/led_twinkle/led_twinkle.gen/sources_1/ip/ila_0/ila_0/ila_0_in_context.xdc] for cell 'peter_ila'
Finished Parsing XDC File [c:/workspace/led_twinkle/led_twinkle.gen/sources_1/ip/ila_0/ila_0/ila_0_in_context.xdc] for cell 'peter_ila'
Parsing XDC File [C:/workspace/led_twinkle/led_twinkle.srcs/constrs_1/new/led_twinkle.xdc]
Finished Parsing XDC File [C:/workspace/led_twinkle/led_twinkle.srcs/constrs_1/new/led_twinkle.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/workspace/led_twinkle/led_twinkle.srcs/constrs_1/new/led_twinkle.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/led_twinkle_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/led_twinkle_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1590.539 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1590.539 ; gain = 0.000
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Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1590.539 ; gain = 25.043
---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tfgg484-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1590.539 ; gain = 25.043
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
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Applied set_property MARK_DEBUG = true for cnt0[4]. (constraint file C:/workspace/led_twinkle/led_twinkle.srcs/constrs_1/new/led_twinkle.xdc, line 11).
Applied set_property KEEP_HIERARCHY = SOFT for peter_ila. (constraint file auto generated constraint).
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 26 Bit Adders := 1
+---Registers :
26 Bit Registers := 1
+---Muxes :
2 Input 26 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1590.539 ; gain = 25.043
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---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1590.539 ; gain = 25.043
---------------------------------------------------------------------------------
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1590.539 ; gain = 25.043
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Start Writing Synthesis Report
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Report BlackBoxes:
+------+--------------+----------+
| |BlackBox name |Instances |
+------+--------------+----------+
|1 |ila_0 | 1|
+------+--------------+----------+
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |ila | 1|
|2 |BUFG | 1|
|3 |CARRY4 | 7|
|4 |LUT1 | 2|
|5 |LUT3 | 6|
|6 |LUT4 | 2|
|7 |LUT6 | 30|
|8 |FDCE | 26|
|9 |IBUF | 2|
|10 |OBUF | 2|
+------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1590.539 ; gain = 25.043
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 1590.539 ; gain = 0.000
Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1590.539 ; gain = 25.043
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1593.570 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1598.223 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: 91a2135
INFO: [Common 17-83] Releasing license: Synthesis
23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1598.223 ; gain = 32.727
INFO: [Common 17-1381] The checkpoint 'C:/workspace/led_twinkle/led_twinkle.runs/synth_1/led_twinkle.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file led_twinkle_utilization_synth.rpt -pb led_twinkle_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Oct 14 17:29:59 2023...