We are thinking of synthesis logic into FPGA but the task is quite complex, We found a new way to do what we want: We generate the jedec file and let the end user burn it into PLD. This brings us the ability to design logic from Quantr-Logic, kick a button, and burn it into PLD.
Since JEDEC is quite human-readable, and students can learn what fuse to burn inside the PLD to form their logic, this experience is great for students to feel what programmable logic does. All they need is a programmer to burn it to chip.
JEDEC hack
The jedec file is easy to decode:
